The display of the contents of a video signal on a digital screen of the LCD type allows to digitize this video signal at a given frequency by means of a main clock signal so as to obtain a set of elementary digital signals. These elementary digital signals are applied to picture elements or pixels which constitute the LCD screen, such that the visual content of the video signal is reproduced.
The main clock signal necessary for such a conversion is usually generated by a phase-locked loop (PLL) which receives at its input a first clock signal having the line frequency of the video signal to be digitized as its frequency, as well as a second clock signal having the frame frequency of the video signal to be digitized as its frequency. The first clock signal allows to define the main clock signal frequency, the frequency thereof being a multiple of the frequency of the first clock frequency. The second clock frequency has for its object to act on the operation of the PLL between two video frames, in particular for making the PLL operate in an open loop during the vertical synchronization pulse.
It is necessary on the one hand to provide said first clock signal at the line frequency, which signal is also referred to as horizontal synchronization signal (Hsync), and on the other hand to provide said second clock signal at the frame frequency, which signal is also referred to as vertical synchronization signal (Vsync).
The video signal comprises synchronization information in addition to the video content, irrespective of what its coding format may be. In particular, it comprises horizontal synchronization pulses marking the start of each video line and vertical synchronization pulses marking the start of each video frame, the latter having to be extracted separately so as to generate the horizontal and vertical synchronization signals.
A method implemented in the circuit referenced AD9888 from Analog Devices is known for extracting these synchronization signals from the video signal.
This method describes a counter which is decremented when the level of the video signal is in a first logic state (for example the logic “low” state corresponding to the synchronization pulses), and which is incremented when the level of the video signal is in a second logic state (for example the “high” logic state). A decremental counting by the counter during a period longer than a reference period, the value of which is directly connected to the duration of the synchronization pulses belonging to the coding format of the video signal, indicates the presence of a synchronization pulse.
The method known from the prior art for extracting the synchronization signals from a video signal has a certain number of limitations.
Since the duration of the synchronization pulses changes with the format of the video, the value of said reference period must be modified whenever the coding format of the video signal changes.
This method includes an identification of the coding format of the video signal, which leads to a complicated implementation of this method in view of the multitude of coding formats that exist. This method of extracting synchronization signals is accordingly not universally applicable because it necessitates a new parameter setting for each known format of the video signal.
On the other hand, the dimensioning of the counter is made difficult by the fact that the duration of the synchronization pulses varies widely from one coding format to another.
Finally, this method cannot be used in cases in which the coding format of the video signal cannot be recognized, for example in the presence of a proprietary coding, because it is impossible then to define said reference period.